Nanoelectronics

Tunnel Field-Effect Transistors

Fig.1. Switching behavior of a conventional MOSFET.

In recent years the power consumption of highly integrated circuits has become one of the major roadblocks for a further increase of integration density and clock speed. Since the dynamic part of the power consumption depends on the supply voltage approximately as (Vdd)3, scaling down Vdd has been the route to decrease the power consumption. However, the turn-on behavior of conventional-type field-effect transistors is determined by the field-effect modulated carrier injection from a thermally broadened Fermi distribution in the source contact (see Fig. 1). As a result, switching is limited to a minimum inverse subthreshold slope of 60mV/dec at room temperature. Provided a ratio between on- and off-state of five orders of magnitude is intended and two thirds of the operational voltage lie in the device’s on-state, a minimum supply voltage of roughly 1V is needed to properly operate the device. This minimum supply voltage cannot be scaled down any further without either sacrificing on-state performance or obtaining excessive off-state leakage, as illustrated in Fig.2. Therefore, for ultra-low power applications a device that shows a superior switching behavior with a steeper inverse subthreshold slope still providing a high on-state performance is highly desirable.

At IHT we study novel device architectures based on band-to-band tunneling in various different materials for the realization of so-called tunnel FETs. In addition, we also investigate nanoelectromechanical FET devices for ultra-low power sensor applications and as steep slope transistors based on band-gap modulation. Our experimental work is supported by simulations using either commercially available software or home-made tools.

Fig.2. Transfer characteristics of a conventional MOSFET (black and red lines) in comparison to a steep slope FET (green line).

Nanowire TFETs

Band-to-band tunnel FETs (TFETs) are considered a promising device architecture since they potentially allow realizing an FET that exhibits an inverse subthreshold slope smaller than 60mV/dec. In fact, a number of experimental devices have recently been reported to exhibit a steep S. However, these device show a steep subthreshold swing only in a narrow gate voltage range while an average S<60mV/dec over several orders of magnitude is needed. In addition, due to the presence of the tunneling barrier, TFETs show an on-state performance inferior compared to conventional FETs. A number of performance boosters have been identified including high-k materials, multi-gate architecture, band-gap engineering etc. Current research activities at IHT include work on nanowire TFETs in top-down fabricated silicon nanowires, III-V nanowires as well as 2D materials. In particular, electrostatic doping of the injecting source contact is investigated where an additional gate in the source contact induces carriers in the contact region. Electrostatic doping will become important in TFETs based on ultrathin nanowires with one-dimensional electronic transport. Reasons for this are a deactivation of dopants in nanostructures and the requirement of a source contact that exhibits a low Fermi energy and a very small screening length (usually obtained with a large doping concentration) at the same time.

Since a properly working TFET requires a small band gap at the tunneling barrier but at the same time a large band gap in the source contact and the channel in order to suppress leakage, heterostructures have recently attracted a great deal of interest for the realization of TFETs. In particular, so-called staggered or even broken band line-ups (as for instance in the InAs-GaSb heterosystem) seem attractive since they hold promise for an excellent on-state performance.

At IHT we study hetero-junction TFETs with simulations and also experimentally. To this end, III-V and silicon nanowires are studied. To facilitate our investigations of III-V nanowires we fabricate buried multi-gate substrates that exhibit three individually addressable gates that enable the gate-controlled creation of device with n-type, p-type and tunnel FET configuration (see below).

 

Devices based on Graphene and 2D-Materials

Graphene and transition-metal-dichalcogenides (TMDs) have recently attracted an increasing attention as material for future nanoelectronics devices. This is due to the fact that both material classes are inherently extremely thin thus enabling ultimately scaled field-effect transistors fabricated based on standard planar processing technologies.

Fig. 3. Combination of cross-section and top view electron micrograph of a buried triple-gate sub-strate with a 30nm graphene nanoribbon.

Graphene is a zero-gap semiconductor but a band gap can be generated when it is patterned into a nanoribbon. This allows adjusting the size of the band gap by lateral patterning of graphene which in turn yields the possibility of band gap engineering that makes graphene highly attractive for TFETs. Furthermore, a band gap can be opened in bilayer graphene by applying a vertical electric field. TMDs on the other hand provide a sizable band gap and are therefore very attractive for logic transistor applications. However, appropriate doping of 2D materials is a delicate task. We therefore use buried triple-gate structures to realize the required doping profiles for the realization of e.g. a tunnel FET. Figure 3 shows an electron micrograph of a buried triple-gate substrate with a 30nm graphene nanoribbon on its surface. Applying different voltages at the three gates enables the realization of n-type, p-type and tunnel FETs.

Fig. 4.Heterostructure consisting of 2D materials stacked on top of each other.

Fig. 4.Heterostructure consisting of 2D materials stacked on top of each other.

In addition, due to their two-dimensional nature TMDs can be stacked on top of each other layer by layer realizing heterostructures. Figure 4 shows a heterostructure consisting of MoS2, hexagonal boron nitride and graphene that can be used to realize e.g. an all-2D FET. We currently study the use of heterostructures consisting of combinations of various 2D materials for optimized TFETs. Furthermore, strain allows manipulating the size of the band gap. This effect can be exploited in various ways, for instance in nano-electromechanical sensor applications or for the realization of a steep-slope NEMS-FET.

 

Sensor Applications

The on- and off-state performance of tunnel FETs depends exponentially on the gate oxide thickness of the device. This strong dependence can be used for sensor applications in e.g. cantilever-based devices. We currently explore the possibility of realizing silicon-based pressure- and cantilever sensors with integrated tunnel FETs for a direct and highly sensitive read-out. In addition, we also study a novel read-out mechanism based on a conventional short channel transistor.

Fig. 4. Lateral Cantilever structure with electrostatic actuation.

Fig. 4. Lateral Cantilever structure with electrostatic actuation.

Device Modeling

We also investigate TFET devices with simulation using either commercial software (COMSOL and TCAD) or home-made tools based on the non-equilibrium Green’s function formalism. Our device modeling activities are closely linked to either our own experimental investigations or are performed in collaboration with partners. Device modeling is done for various kinds of ultrathin-body devices such as conventional-type nanowire FETs, SOI Schottky-barrier MOSFET as well as carbon nanotube/graphene/TMD FETs and tunnel FETs. Our work aims at exploring the benefits of low-dimensional structures for conventional field-effect transistors, Schottky-barrier MOSFETs as well as tunnel FETs.