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Solid State Technology

(V2/Ü1, winter term, MSc-level)

After a brief introduction into solid state physics aspects of semiconductors, their crystal structure and manufacturing process, this lecture deals with advanced concepts of CMOS fabrication technologies such as modern projection lithography, electron-beam lithography, dry and wet chemical etching, high-k dielectric materials, epitaxy and self-organized growth. The lecture is offered regularly during the winter term.

Contact person: Birger Berghoff

Lecture notes, homework assignments and addition course material can be downloaded from L²P

Nanoelectronics Devices – Physics, Modelling and Simulation

(V2/Ü1, winter term, MSc-level, language of instruction: English)

This lecture starts with revisiting the classical MOSFET explaining Moore’s law, the scaling of transistors and the appearance and impact of short-channel-effects (SCE). Strategies to circumvent SCE such as nanowire transistors, carbon nanotube and graphene devices will be introduced and discussed in detail. Furthermore, novel device concepts such as Schottky-barrier MOSFETs and tunnel FETs will be studied. In addition to simple models that allow predicting the device performance based on ballistic electronic transport this lecture gives an introduction into device simulation techniques, in particular the non-equilibrium Green’s function formalism. The lecture will be offered regularly during winter terms and is the prerequisite for the course “Quantum Simulation of Carbon Nanotube and Graphene Nanoribbon Field-Effect Transistors”.

Contact person: Thomas Grap

Lecture notes, lecture videos, homework assignments and addition course material can be downloaded from L²P

Quantum Simulation of Carbon Nanotube and Graphene Nanoribbon Field-Effect Transistors

(V2/Ü1, summer term, MSc-level, language of instruction: English)

Within the course students develop a simple tool for the simulation of quantum transport in nanoscale field-effect transistor devices based on a self-consistent solution of the Poisson and Schrödinger equation. To this end, the non-equilibrium Green’s function formalism is used. After a brief repetition/introduction, students will write their own code in MATLAB. The simulation tool enables students to study the dependence of the electrical behavior of nanoscale field-effect transistors on their geometry and material in use. Due to a limited availability of work space and to ensure appropriate support by our personnel the course is limited to roughly 16 students. Prerequisite is a course such as “Nanoelectronics Devices – Physics, Modelling and Simulation” or similar.

Contact person: Prof. Joachim Knoch

Lecture notes, homework assignments and addition course material can be downloaded from L²P

Fabrication and Characterization of Nanoelectronic Devices

(V2/Ü1, MSc-level, summer term, language of instruction: English)

The course starts with a short repetition of MOSFETs, their layout and fabrication processes. Students will partly design the individual devices as well as circuit elements such as inverters and logic gates. Afterwards each participant will fabricate his/her own chip including n- as well as p-type MOSFETs in the institute’s clean room facility. Finally, the devices and circuit elements will be characterized with electrical measurements. Instead of a written test, students are required to write a scientific paper including the theoretical background, the fabrication process, the characterization as well as interpretation of the measurements. Due to space limitations in our clean room this course will be limited to roughly 15-18 students. The course takes place every other week for 4.5h. Prerequisites to take part are a profound knowledge of semiconductor fabrication technologies (such as the course “Solid State Technology”).

Contact person: Prof. Joachim Knoch

Lecture notes, homework assignments and addition course material can be downloaded from L²P

Laboratory Classes

Fabrication and Characterization of Pseudo-MOSFETs

(BSc-level, winter term)

With the advent of silicon-on-insulator (SOI) and in particular strained SOI there is a need to quickly get access to the mobility of carriers in such SOI films in order to qualify the substrates and to check the substrate fabrication processes. Pseudo-MOSFETs are a straightforward way of fabricating full three-terminal MOSFETs that allows extracting the mobility, a measure for the electronic transport properties in the SOI film. In a pseudo-MOSFET, the buried oxide of the SOI substrate is used as the gate dielectric and the handle wafer as a large area back-gate. As a result, a working device is obtained after mesa insulation of the active area and the formation of source/drain contacts. During this lab training students will actively fabricate and characterize their own pseudo-MOSFET devices and will extract relevant electrical parameters such as the carrier mobility etc.

Contact person: Birger Berghoff