Multi-Gate Devices

Atomic force microscopy image of a WSe2 flake on top of a burried multi-gate structure Copyright: © IHT RWTH Atomic force microscopy image of a WSe2 flake on top of a burried multi-gate structure

Field-effect transistors are a suitable vehicle to study the electronic properties of alternative materials (as replacement or add-on to silicon) such as carbon nanotubes, graphene or transition metal dichalcogenides. However, since it is often not known how appropriate doping can be established and to obtain the ability to adjust a certain potential landscape within the device, gate electrodes are used to realize electrostatic doping [1]. At Institute of Semiconductor Electronics we work on the fabrication of buried multi-gate substrates that serve as a platform to study various different nanostructures. Exemplarily, the figure on the left shows an atomic force microscopy image of a WSe2 flake contacted with nickel source and drain contacts on top of a buried triple-gate substrate.

  Scanning electron micrograph of of a buried multi-gate structure. Copyright: © IHT RWTH Scanning electron micrograph of of a buried multi-gate structure.

The image shows a scanning electron microscopy image cross section of buried triple-gate substrate. Based on such devices we were recently able to demonstrate n-type and p-type transistor operation as well as the operation as band-to-band tunnel field-effect transistors of a single WSe2 flake [2].

  Copyright: © IHT RWTH Top-view of an InAs nanowire field-effect transistor on top of a buried multi-gate substrate (scanning electron micrograph).  

In order to realize more complicated potential landscapes, for example to study coupled quantum dots in various nanostructures we also fabricate buried multi-gate substrates. Instead of patterning multiple gates on top of a nanostructure with, e.g., electron-bea, lithography and lift-off, buried mutigate substrates allow using thin-film depostion processes to determine the gate lenght and the inter-gate distance providing superior dimensional control as well as facilitating to scale the gate length down to the sub-5 nm regime. At the same time, we are able to contact all gate electrodes individually. The figure on the left shows scanning electron micrographs pf a nanowier FET on top of a buried multi-gate substrate. The various leads to contact the indiovidual gate layer are clearly visible.

  Cross-section of an InAs nanowire field-effect transistor. Copyright: © IHT RWTH Cross-section of an InAs nanowire field-effect transistor on a burried multi-gate substrate (scanning electron micrograph).  

Instead of integrating the various gate electrodes into a substrate we also work on the realization of multi-top-gate structures with nanoscale dimensions exploiting processes such as spacer and double spacer lithography combined with damascene processes. The aim of this intiative is the realization of coupled quantum dot structures on "conventional" semiconductor platforms such as AlGaAs/GaAs and Si/SiGe heterostructures.

Finally, our work also encompasses the fabrication and characterization of nanoscale field-effect transistors that operate at cryogenic temperatures and extremely low power level. The overall goal is the development of a dedicated cryogenic CMOS technology which could be used fort he realisation of classical control circuits for quantum information systems.


[1] J. Knoch and M.R. Müller, "Electrostatic Doping - Controlling the Properties of Carbon-Based FETs With Gates", IEEE Trans. Nanotechnol. 13, 1044 (2014).

[2] M.R. Müller, R. Salazar, S. Fathipour, H. Xu, K. Kallis, U. Künzelmann, A. Seabaugh, J. Appenzeller and J. Knoch, "Gate-controlled WSe2 transistors using a buried triple-gate structure", Nanoscale Res. Lett. 11, 512 (2016).

[3] T. Grap, F. Riederer, C. Gupta and J. Knoch, "Buried Multi-Gate InAs-Nanowire FETs", European Solid State Res. Conf. 2017.


Alternatives for Doping

Doping is one of the most important techniques and basically the reason why virtually all semiconductor devices work. However, at the nanoscale doping becomes increasingly difficult. The reasons for this fact are manifold: For instance, when scaling a nanostructure down it was shown that dopants get deactivated due to a dielectric mismatch of the nanostructure and its surrouding [1]. At even smaller scales, quantum confinement leads to an increase of the ionization energy of dopants (and thus to deactivation). Moreover, in nanoscale devices only a handful of dopants are present that lead to random dopant related fluctuations and variability. In addition to this, more subtle effects such as finding the optimum amount of dopants in band-to-band tunnel field-effect transistors [2] may also become important. Replacing the doped regions with metals is not necessarily an option since, first, a Schottky-barrier usually builds up at the metal-semiconductor interface that deteriorates current flow and, second, metal-induced gap states lead to a high density of states within the band-gap, which means that the band gap is strongly deteriorated at the metal interface; this is the reason for ambipolar behavior of Schottky-barrier field-effect transistors.

As an alternative for doping we employ ultrathin insulators inserted in-between the metal and the semiconductor. If an appropriate insulator of appropriate thickness is chosen, dangling bonds at the silicon surface are saturated and at the same time metal-induced gap states are suppressed. A well suited insulator is silicon nitride since it can be grown in a self-terminating way by rapid thermal processing. Sub-1 nm thicknesses can be manufactured reliably and reproducibly. Using simple so-called pseudo-MOSFET structures we were able to show that such thin silicon nitride layers lead to an improved on-state performance and to a suppression of the ambipolar behavior. This means that the metal-silicon nitride-silicon stacks behave similar to a doped semiconductor with an prestine band gap. With appropriate work function of the contact metal, n- and p-„doped“ silicon can be realized and we were able to show n-type as well as p-type field-effect transistors with aluminum and platinum as contact metals [3].

  Ultrathin-body SOI Copyright: © IHT RWTH Transmission electron micrograph of a 1.7 nm thin silicon layer embedded into SiO2.

Replacing doped source and drain regions with a metal-silicon nitride stack is an attractive approach since this also allows decreasing the parasitic contact resistance. However, the source and drain metallic contacts need to be insulated from the actual gate electrode and thus, a means that mimics doping based on insulating layers is highly desirable. To this end, we started investigations towards the impact of conventional insulators on ultrathin silicon-on-insulator layers exploiting a quantum chemical shift of the respective energy levels.


[1] M.T. Björk, H. Schmid, J. Knoch, H. Riel and W. Riess, "Donor Deactivation in Silicon Nanostructures", Nature Nanotechnol. 4, 103 (2009).

[2] J. Knoch, S. Mantl and J. Appenzeller, "Impact of the dimensionality on the performance of tunneling FETs: Bulk versus one-dimensional devices", Solid-State Electron. 51, 572 (2007).

[3] S. Fischer, H.I. Kremer, B. Berghoff, T. Maß, T. Taubner and J. Knoch, "Dopant‐free complementary metal oxide silicon field effect transistors", phys. stat. sol. a 213, 1494 (2016).


Simulations of Nanoscale Field-Effect Transistors

NEGF Simulations Copyright: © IHT RWTH Local density of states within a conventional field-effect transistor computed with NEGF.

We also perform simulation studies on the electrical behavior of field-effect transistors based on nanowires and nanotubes [1,2] as well as 2D materials [3]. In particular, Schottky-barrier [4] and band-to-band tunnel field-effect transistors [5,6] are being investigated. These simualtions are mostly done with home-made simulations tools based on self-consistent Poisson-Schrödinger simulations using the non-equilibrium Green’s function formalism (NEGF). The aim of our simulations is to explain novel effects or to support experimental studies. For instance, the first experimental demonstration of a field-effect transistor showing an inverse subthreshold slope smaller 60 mV/dec was verified and the transport mechanism explained by comparing simulations with experimental data [5].

[1] J. Knoch and J. Appenzeller, "Tunneling Phenomena in Carbon Nanotube Field-Effect Tranistors", phys. stat. sol. a 205, 679 (2008).

[2] Z. Chen, J. Appenzeller, J. Knoch, Y.-M. Lin and P. Avouris, "The role of metal− nanotube contact in the performance of carbon nanotube field-effect transistors", Nano Lett. 5, 1497 (2005).

[3] J. Knoch, Z. Chen and J. Appenzeller, "Properties of Metal-Graphene Contacts", IEEE Trans. Nanotechnol. 11, 513 (2012).

[4] J. Knoch, M. Zhang, S. Mantl and J. Appenzeller, "On the performance of single-gated ultrathin-body SOI Schottky-barrier MOSFETs", IEEE Trans. Electron Dev. 53, 1668 (2006).

[5] J. Appenzeller, Y.-M. Lin, J. Knoch and P. Avouris, "Band-to-band tunneling in carbon nanotube field-effect transistors", Phys. Rev. Lett. 93, 196805 (2004).

[6] J. Knoch, "Chapter eight – Nanowire Tunneling Field-Effect Transistors", Semicond. Semimet. 94, 273 (2016).