Ge(Sn)-based vertical gate-all-around nanowire MOSFETs and inverters for low power logic
Liu, Mingshan; Knoch, Joachim (Thesis advisor); Grützmacher, Detlev (Thesis advisor)
Aachen : RWTH Aachen University (2021)
Dissertation / PhD Thesis
Dissertation, Rheinisch-Westfälische Technische Hochschule Aachen, 2021
Over the past half century, transistor miniaturization is the main driver to enhance Si complementary metal-oxide-semiconductor (CMOS) performance generation by generation in terms of shrinking the gate length, gate width, and oxide thickness, denoted as the Moore’s Law. However, continuous advances of traditional planar devices hit a bottleneck because of power dissipation, packing density, electrostatic controllability and variability limitations. Approaches utilizing alternative channel materials and new device architecture, are proposed to further extend CMOS roadmap. Ge and newly emerging GeSn semiconductors are promising candidates because they offer high carrier mobilities, small and tunable bandgaps, and easy integration on Si wafers. Moreover, the migration of transistor architecture from conventional planar structure to 3D FinFET, and eventually to gate-all-around (GAA) nanowire device has been witnessed, which necessitates superior gate electrostatics and good immunity against short-channel effects. As is theoretically predicted, vertical GAA nanowire transistors provide further scalability, more layout efficiency and less power consumption compared to FinFETs and horizontal nanowire transistors, which are considered as the ultimate structure for the classical CMOS scaling. This thesis investigates the application of vertical nanowires in the GeSn/Ge p-type and n-type MOSFETs and evaluates the feasibility of vertical nanowire transistors in logic circuit applications. In this regard, key process modules are examined: (i) An optimized vertical nanowire etching method for excellent verticality and smooth sidewalls is developed and digital etching, similar to atomic layer etching is applied to achieve nanowires with sub-20 nm diameters; (ii) Dielectric stacks with post-oxidation passivation are applied to reduce density of interface traps (Dit) between the dielectric and Ge(Sn) channel; (iii) Both p-type and n-type Ohmic contacts for Ge(Sn) are accessed for high performance MOSFETs. Vertical Ge GAA nanowire pMOSFETs by a top-down approach are experimentally demonstrated for the first time, which exhibit excellent subthreshold properties. The superiority of gate electrostatic integrity is affirmed by the dependence of electrical performance on nanowire diameter scaling. The contact on the nanowire tip is revealed as the roadblock for vertical nanowire transistors. With the performance comparison by swapping source and drain, it is concluded that the doping deactivation effect in small nanowires is responsible for the performance asymmetry. Furthermore, low temperature I-V characterization manifests a typical temperature-dependence of subthreshold swing (SS), the deviation between experimental data and ideal SS lies primarily in Dit and source resistance. Threshold voltage with temperatures depicts linear behaviors with slopes of 1.6 mV/K and 3 mV/K for 45 nm and 65 nm nanowire pMOSFETs, respectively. To achieve enhanced on-state performance, Ge0.92Sn0.08/Ge GAA nanowire pMOSFETs are fabricated by growing GeSn as the top layer for a lowered contact resistivity. The strain distribution and band structure at the GeSn/Ge interface in the quasi-1D nanowires are calculated, which brings benefits for the key electrical figures of merits. With a scaled EOT of ~2 nm, GeSn/Ge nanowire pMOSFETs achieve low SS of 67 mV/dec, record high Gm,ext of ~870 µS/µm and the best quality factor Q of ~ 9.1 among all reported GeSn-based pMOSFETs.To achieve high performance GeSn/Ge nMOSFETs, great challenges e.g. strong Fermi level EF pinning, a large Dit, need to be addressed. In this context, vertical Ge/Ge0.95Sn0.05/Ge GAA nanowire nMOSFETs are fabricated and characterized. GeSn-channel nanowire nMOSFETs with decent electrical performance outperform Ge control devices, which emphasizes the advantage of high-mobility GeSn as the channel. With the performance-symmetrical Ge/Ge0.95Sn0.05/Ge nanowire nMOSFETs and Ge0.92Sn0.08/Ge nanowire pMOSFETs, the first proof of concept for a GeSn-based hybrid CMOS inverter is realized with a high voltage gain of ~18 at VDD=0.8V. All in all, the vertical nanowire architecture along with Ge(Sn) material could potentially enable CMOS applications beyond 5 nm nodes.
- DOI: 10.18154/RWTH-2021-02244
- RWTH PUBLICATIONS: RWTH-2021-02244