Selected Journal Publications
Lateral electrochemical metallization (ECM) cells are fabricated with a combined spacer/damascene process. The process allows the realization of nanoscale geometrical distances between the two electrodes independent of lithography. Such lateral ECM cells are an essential part in a reconfigurable interconnect system that may yield a strongly increased connectivity in artificial neural networks. The lateral cells show memristive properties comparable to vertical cells with switching voltages in the range of –1.5V to 2.5V. The influence of electrode line edge roughness on SET kinetics of such lateral cells is investigated via kinetic Monte Carlo simulations, finding a minor influence on SET time variability.
Area-dependent memristive devices such as Al / Pr 0.7 Ca 0.3 MnO 3 (PCMO) stacks are highly interesting candidates for synapses in neuromorphic circuits due to their gradual switching properties, their reduced variability and the possibility to tune the resistance with the device area. However, due to the complexity of the different processes taking place, the electronic and ionic transport in theses devices is so far only poorly understood and physical compact models to simulate their behavior are missing so far. We developed a mathematical description of the dynamics of theses devices based on a simple two-resistor model that reproduces the device behavior very well. Based on x-ray photoelectron spectroscopy and impedance spectroscopy we assign the two resistors to the AlO x layer and a depletion zone at the Pr 0.7 Ca 0.3 MnO 3 layer, respectively. We assign the parameters used within the mathematical model to physical parameters and make use of them in order to explain the dynamics of the switching processes during the SET and RESET process in different voltage regimes. For both poly- and single crystalline PCMO thin film devices, oxygen migration between the AlO x and the PCMO depletion zone is responsible for the resistance change. However, the dynamics differ significantly due to the increased mobility of oxygen vacancies with increasing defect density in the case of the polycrystalline samples. Moreover, we observe volatile subloops in our current-voltage curves, which vanish within millisecond time scale. Based on our two-resistor model and the band diagram derived from spectroscopic measurements, we assign these subloops to the injection of electrons into traps within the AlO x barrier.
The electronic structure of SiO2 versus Si3N4-coated low nanoscale intrinsicsilicon (Si) shifts away from versus toward the vacuum level Evac, originating from the Nanoscale Electronic Structure Shift Induced by Anions at Surfaces(NESSIAS). Using the quantum chemical properties of the elements involved to explain NESSIAS, an analytic parameter L is derived to predict the highest occupied energy level of Si nanocrystals (NCs) as verified by various hybrid-density functional calculations and NC sizes. First experimental data of Si nanowells (NWells) embedded in SiO2 versus Si3N4 were measured by X-ray absorption spectroscopy in total fluorescence yield mode (XAS-TFY), complemented by ultraviolet photoelectron spectroscopy (UPS).
Herein, cryogenic fi eld-effect transistors (FETs) are discussed. In particular, the saturation of the subthreshold swing due to band tailing is studied. It is shown with simulations and experiments that engineering of the oxide-channel inter faces and a strong increase of the gate oxide capacitance are effective in improving the switching behavior of the device. The implication of scaling the oxide capacitance on the power consumption of cryogenic devices is investi gated, too. Furthermore, an alternative for conventional doping in cryogenic transistors is discussed. Based on synchrotron X-Ray absorption spectroscopy at total fl uorescence (XAS-TFY) and ultraviolet photoemission spectroscopy (UPS) measurements, it is shown experimentally that in true nanoscale devices, a simple SiO 2 coating yields a shift of the conduction band that is equivalent to a very high dopant concentration. As a result, nanoscale cryogenic steep slope FETs with strongly improved electrical characteristics become feasible.
The continued downscaling of silicon CMOS technology presents challenges for achieving the required low power consumption. While high mobility channel materials hold promise for improved device performance at low power levels, a material system which enables both high mobility n-FETs and p-FETs, that is compatible with Si technology and can be readily inte grated into existing fabrication lines is required. Here, we present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si. While the p-FET transconductance is increased to 850 mS/mm by exploiting the small band gap of GeSn as source yielding high injection velocities, the mobility in n-FETs is increased 2.5-fold compared to a Ge reference device, by using GeSn as channel material. The potential of the material system for a future beyond Si CMOS logic and quantum computing applications is demonstrated via a GeSn inverter and steep switching at cryogenic temperatures, respectively.
In this work, we study experimentally the impact of different gate dielectric stacks on the subthreshold behavior of cryogenic MOSFETs. While in room temperature devices, silicon nitride deteriorates the off-state of MOSFETs it turns out that at cryogenic temperatures an appropriately thin, grown silicon nitride layer in combination with a high-k gate dielectric counteracts the saturation of the inverse subthreshold slope and inflection phenomena. As a result, steep slope cryogenic MOSFETs with strongly improved subthreshold behavior are demonstrated.
Fully silicided source/drain Si gate-all-around (GAA) nanowire (NW) p-FETs with NW diameter of 5 nm are fabricated and characterized from room temperature (RT) down to 5.5 K. Thanks to the improved electrostatics by the scaled NW and 3D GAA structure, close to ideal transfer characteristics are obtained at both RT and 5.5 K with a sharp switching. Benefiting from less defects in Si created by the implantation into silicide (IIS) process, the band tail effects and neutral defects scattering are suppressed. Therefore, the fabricated Si GAA NW p-FETs provide very low subthreshold swing SS of 3.4 mV/dec in the weak inversion region and an average SSth of 14 mV/dec measured from the off-state to the threshold voltage, as well as an improved transconductance Gm at 5.5 K.
This article studies the sub-linearity of the output characteristics measured in Schottky-barrier metal- oxide semiconductor field-effect transistors with simula tions and experiments. It is shown that the sub-linearity is not due to the forward-biased Schottky diode at the drain contact interface but due to the drain bias impact on the source-side Schottky-barrier, resulting in an increased carrier injection with increasing drain–source voltage. The simulation results are confirmed with the measurements of fabricated dual-gate Schottky-barrier transistors.
This paper addresses issues related to cracking and blisters in deposited films encountered in a lift-off process with electron beam evaporation and a bilayer PMMA resist system. The impact of charged particles, i.e., electrons and ions, is investigated using an electron beam evaporation chamber equipped with ring-magnets and a plate electrode placed in front of the sample. By replacing the plate electrode with a hollow metallic cylinder, the modified evaporation setup utilizing passive components allows complete elimination of resist shrinkage and bubble formation yielding near perfect deposition results for a large variety of different materials.
Impurity doping in silicon (Si) ultra-large-scale integration is one of the key challenges which prevent further device miniaturization. Using ultraviolet photoelectron spectroscopy and X-ray absorption spectroscopy in the total fl uorescence yield mode, we show that the lowest unoccupied and highest occupied electronic states of ≤ 3 nm thick SiO2-coated Si nanowells shift by up to 0.2 eV below the conduction band and ca. 0.7 eV below the valence band edge of bulk silicon, respectively. This nanoscale electronic structure shift induced by anions at surfaces (NESSIAS) provides the means for low nanoscale intrinsic Si (i-Si) to be flooded by electrons from an external (bigger, metallic) reservoir, thereby getting highly electron- (n-) conductive. While our findings deviate from the behavior commonly believed to govern the properties of silicon nanowells, they are further con fi rmed by the fundamental energy gap as per nanowell thickness when compared against published experimental data. Supporting our fi ndings further with hybrid density functional theory calculations, we show that other group IV semiconductors (diamond, Ge) do respond to the NESSIAS eff ect in accord with Si. We predict adequate nanowire cross-sections (X-sections) from experimental nanowell data with a recently established crystallographic analysis, paving the way to undoped ultrasmall silicon electronic devices with signifi cantly reduced gate lengths, using complementary metal− oxide − semiconductor-compatible materials.
We investigate the operation modes of a dual-gate reconfigurable field-effect transistor (RFET). To this end, dual-gate silicon-nanowire FETs are fabricated based on anisotropic wet etching of silicon and nickel silicidation yielding silicide-nanowire Schottky junctions at source and drain. We compare the program gate at source (PGAS) with the more usual program gate at drain (PGAD) operation mode. While in PGAD mode, ambipolar operation is suppressed, switching is deteriorated due to the injection through a Schottky barrier. Operating the RFET in PGAS mode yields a switching behavior close to a conventional MOSFET. This, however, needs to be traded off against strongly nonlinear output characteristics for small bias voltages. Our measurement results are supported by transport simulations employing a nonequilibrium Green's function approach.
Harvesting the full potential of single-crystal semi conductor nanowires (NWs) for advanced nanoscale fi eld-e ff ect transistors (FETs) requires a smart combination of charge control architecture and functional semiconductors. In this article, high- performance vertical gate-all-around NW p-type FETs (p-FETs) are presented. The device concept is based on advanced Ge0.92Sn0.08/Ge group IV epitaxial heterostructures, employing quasi − one-dimensional semiconductor NWs fabricated with a top- down approach. The advantage of using a heterostructure is the possibility of electronic band engineering with band o ff sets tunable by changing the semiconductor stoichiometry and elastic strain. The use of a Ge0.92Sn0.08 layer as the source in GeSn/Ge NW p- FETs results in a small subthreshold slope of 72 mV/dec and a high ION /IOFF 106. A ~32% drive current enhancement is obtained compared to the vertical Ge homojunction NW control devices. More interestingly, the drain-induced barrier lowering is much smaller with GeSn instead of Ge as the source. The general improvement of the transistor ’ s key fi gures of merits originates from the valence band o ff set at the Ge0.92Sn0.08/Ge heterojunction, as well as from a smaller NiGeSn/GeSn contact resistivity.
The n-type doping of Ge is a self-limiting process due to the formation of vacancy-donor complexes (D n V with n ≤ 4) that deactivate the donors. This work unambiguously demonstrates that the dissolution of the dominating P 4 V clusters in heavily phosphorus-doped Ge epilayers can be achieved by millisecond-flash lamp annealing at about 1050 K. The P 4 V cluster dissolution increases the carrier concentration by more than three-fold together with a suppression of phosphorus diffusion. Electrochemical capacitance–voltage measurements in conjunction with secondary ion mass spectrometry, positron annihilation lifetime spectroscopy and theoretical calculations enabled us to address and understand a fundamental problem that has hindered so far the full integration of Ge with complementary-metal-oxide-semiconductor technology.
In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl2 -based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high ION /IOFF ratio of 2.1 × 106 . The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q ·ln10 values stems from the density of interface traps (Dit). Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors.
Conventional impurity doping of deep nanoscale silicon (dns-Si) used in ultra large scale inte gration (ULSI) faces serious challenges below the 14 nm technology node. We report on a new fundamental effect in theory and experiment, namely the electronic structure of dns-Si experiencing energy offsets of ca. 1 eV as a function of SiO 2 - vs. Si 3 N 4 -embedding with a few monolayers (MLs). An interface charge transfer (ICT) from dns-Si specific to the anion type of the dielectric is at the core of this effect and arguably nested in quantum-chemical properties of oxygen (O) and nitrogen (N) vs. Si. We investigate the size up to which this energy offset defines the electronic structure of dns-Si by density functional theory (DFT), considering interface orientation, embedding layer thick ness, and approximants featuring two Si nanocrystals (NCs); one embedded in SiO 2 and the other in Si 3 N 4 . Working with synchrotron ultraviolet photoelectron spectroscopy (UPS), we use SiO 2 - vs. Si 3 N 4 -embedded Si nanowells (NWells) to obtain their energy of the top valence band states. These results confirm our theoretical findings and gauge an analytic model for projecting maximum dns-Si sizes for NCs, nanowires (NWires) and NWells where the energy offset reaches full scale, yielding to a clear preference for electrons or holes as majority carriers in dns-Si. Our findings can replace impurity doping for n/p-type dns-Si as used in ultra-low power electronics and ULSI, eliminating dopant related issues such as inelastic carrier scattering, thermal ionization, clustering, out-diffusion and defect generation. As far as majority carrier preference is concerned, the elimination of those issues effectively shifts the lower size limit of Si-based ULSI devices to the crystalization limit of Si of ca. 1.5 nm and enables them to work also under cryogenic conditions.
We present a record-high solar-to-hydrogen conversion efficiency (STH) for monolithic all-silicon multi-junction solar devices. The device is based on an interdigitated back-contact silicon solar cell, in which the p- and n-regions are connected in a combination of series and parallel contacts, in order to triple the photovoltage compared to a single-junction cell. Our best device provides an open-circuit voltage of 1.99 V, larger than the water redox potential of 1.23 V plus overpotentials at the electrodes, as well as a short-circuit current density of 12.6 mA/cm2. Coupled to a sulphuric acid electrolysis system, with platinum and ruthenium dioxide electrodes, our device shows an STH of 14.5% at 1.63 V.
In the present paper, we show tungsten diselenide (WSe 2 ) devices that can be tuned to operate as n -type and p -type field-effect transistors (FETs) as well as band-to-band tunnel transistors on the same flake. Source, channel, and drain areas of the WSe 2 flake are adjusted, using buried triple-gate substrates with three independently controllable gates. The device characteristics found in the tunnel transistor configuration are determined by the particular geometry of the buried triple-gate structure, consistent with a simple estimation of the expected off-state behavior.
For the investigation of 2D layered materials such as graphene, transition-metal dichalcogenides, boron nitride, and their heterostructures, dedicated substrates are required to enable unambiguous identification through optical microscopy. A systematic study is conducted, focusing on various 2D layered materials and substrates. The simulated colors are displayed and compared with microscopy images. Additionally, the issue of defining an appropriate index for measuring the degree of visibility is discussed. For a wide range of substrate stacks, layer thicknesses for optimum visibility are given along with the resulting sRGB colors. Further simulations of customized stacks can be conducted using our simulation tool, which is available for download and contains a database featuring a wide range of materials.