Area-dependent memristive devices such as $\mathrm{Al}/{\mathrm{Pr}}_{0.7}{\mathrm{Ca}}_{0.3}{\mathrm{MnO}}_3$ (PCMO) stacks are highly interesting candidates for synapses in neuromorphic circuits due to their gradual switching properties, their reduced variability and the possibility to tune the resistance with the device area. However, due to the complexity of the different processes taking place, the electronic and ionic transport in theses devices is so far only poorly understood and physical compact models to simulate their behavior are missing so far. We developed a mathematical description of the dynamics of theses devices based on a simple two-resistor model that reproduces the device behavior very well. Based on x-ray photoelectron spectroscopy and impedance spectroscopy we assign the two resistors to the ${\mathrm{AlO}}_x$ layer and a depletion zone at the ${\mathrm{Pr}}_{0.7}{\mathrm{Ca}}_{0.3}{\mathrm{MnO}}_3$ layer, respectively. We assign the parameters used within the mathematical model to physical parameters and make use of them in order to explain the dynamics of the switching processes during the SET and RESET process in different voltage regimes. For both poly- and single crystalline PCMO thin film devices, oxygen migration between the ${\mathrm{AlO}}_x$ and the PCMO depletion zone is responsible for the resistance change. However, the dynamics differ significantly due to the increased mobility of oxygen vacancies with increasing defect density in the case of the polycrystalline samples. Moreover, we observe volatile subloops in our current-voltage curves, which vanish within millisecond time scale. Based on our two-resistor model and the band diagram derived from spectroscopic measurements, we assign these subloops to the injection of electrons into traps within the ${\mathrm{AlO}}_x$ barrier.

Herein, cryogenic fi eld-effect transistors (FETs) are discussed. In particular, the saturation of the subthreshold swing due to band tailing is studied. It is shown with simulations and experiments that engineering of the oxide-channel inter faces and a strong increase of the gate oxide capacitance are effective in improving the switching behavior of the device. The implication of scaling the oxide capacitance on the power consumption of cryogenic devices is investi gated, too. Furthermore, an alternative for conventional doping in cryogenic transistors is discussed. Based on synchrotron X-Ray absorption spectroscopy at total fl uorescence (XAS-TFY) and ultraviolet photoemission spectroscopy (UPS) measurements, it is shown experimentally that in true nanoscale devices, a simple SiO ₂ coating yields a shift of the conduction band that is equivalent to a very high dopant concentration. As a result, nanoscale cryogenic steep slope FETs with strongly improved electrical characteristics become feasible.

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In this work, we study experimentally the impact of different gate dielectric stacks on the subthreshold behavior of cryogenic MOSFETs. While in room temperature devices, silicon nitride deteriorates the off-state of MOSFETs it turns out that at cryogenic temperatures an appropriately thin, grown silicon nitride layer in combination with a high-k gate dielectric counteracts the saturation of the inverse subthreshold slope and inflection phenomena. As a result, steep slope cryogenic MOSFETs with strongly improved subthreshold behavior are demonstrated.

This article studies the sub-linearity of the output characteristics measured in Schottky-barrier metal- oxide semiconductor field-effect transistors with simula tions and experiments. It is shown that the sub-linearity is not due to the forward-biased Schottky diode at the drain contact interface but due to the drain bias impact on the source-side Schottky-barrier, resulting in an increased carrier injection with increasing drain–source voltage. The simulation results are confirmed with the measurements of fabricated dual-gate Schottky-barrier transistors.

Impurity doping in silicon (Si) ultra-large-scale integration is one of the key challenges which prevent further device miniaturization. Using ultraviolet photoelectron spectroscopy and X-ray absorption spectroscopy in the total fl uorescence yield mode, we show that the lowest unoccupied and highest occupied electronic states of ≤ 3 nm thick SiO₂-coated Si nanowells shift by up to 0.2 eV below the conduction band and ca. 0.7 eV below the valence band edge of bulk silicon, respectively. This nanoscale electronic structure shift induced by anions at surfaces (NESSIAS) provides the means for low nanoscale intrinsic Si (i-Si) to be flooded by electrons from an external (bigger, metallic) reservoir, thereby getting highly electron- (n-) conductive. While our findings deviate from the behavior commonly believed to govern the properties of silicon nanowells, they are further con fi rmed by the fundamental energy gap as per nanowell thickness when compared against published experimental data. Supporting our fi ndings further with hybrid density functional theory calculations, we show that other group IV semiconductors (diamond, Ge) do respond to the NESSIAS eff ect in accord with Si. We predict adequate nanowire cross-sections (X-sections) from experimental nanowell data with a recently established crystallographic analysis, paving the way to undoped ultrasmall silicon electronic devices with signifi cantly reduced gate lengths, using complementary metal− oxide − semiconductor-compatible materials.

Harvesting the full potential of single-crystal semi conductor nanowires (NWs) for advanced nanoscale fi eld-e ff ect transistors (FETs) requires a smart combination of charge control architecture and functional semiconductors. In this article, high- performance vertical gate-all-around NW p-type FETs (p-FETs) are presented. The device concept is based on advanced Ge_0.92Sn_0.08/Ge group IV epitaxial heterostructures, employing quasi − one-dimensional semiconductor NWs fabricated with a top- down approach. The advantage of using a heterostructure is the possibility of electronic band engineering with band o ff sets tunable by changing the semiconductor stoichiometry and elastic strain. The use of a Ge_0.92Sn_0.08 layer as the source in GeSn/Ge NW p- FETs results in a small subthreshold slope of 72 mV/dec and a high I_ON /I_OFF 10⁶. A ~32% drive current enhancement is obtained compared to the vertical Ge homojunction NW control devices. More interestingly, the drain-induced barrier lowering is much smaller with GeSn instead of Ge as the source. The general improvement of the transistor ’ s key fi gures of merits originates from the valence band o ff set at the Ge_0.92Sn_0.08/Ge heterojunction, as well as from a smaller NiGeSn/GeSn contact resistivity.

In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl₂ -based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high I_ON /I_OFF ratio of 2.1 × 10⁶ . The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q ·ln10 values stems from the density of interface traps (D_it). Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors.

We present a record-high solar-to-hydrogen conversion efficiency (STH) for monolithic all-silicon multi-junction solar devices. The device is based on an interdigitated back-contact silicon solar cell, in which the p- and n-regions are connected in a combination of series and parallel contacts, in order to triple the photovoltage compared to a single-junction cell. Our best device provides an open-circuit voltage of 1.99 V, larger than the water redox potential of 1.23 V plus overpotentials at the electrodes, as well as a short-circuit current density of 12.6 mA/cm². Coupled to a sulphuric acid electrolysis system, with platinum and ruthenium dioxide electrodes, our device shows an STH of 14.5% at 1.63 V.

For the investigation of 2D layered materials such as graphene, transition-metal dichalcogenides, boron nitride, and their heterostructures, dedicated substrates are required to enable unambiguous identification through optical microscopy. A systematic study is conducted, focusing on various 2D layered materials and substrates. The simulated colors are displayed and compared with microscopy images. Additionally, the issue of defining an appropriate index for measuring the degree of visibility is discussed. For a wide range of substrate stacks, layer thicknesses for optimum visibility are given along with the resulting sRGB colors. Further simulations of customized stacks can be conducted using our simulation tool, which is available for download and contains a database featuring a wide range of materials.